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Add missing Sysbench pass/fail logic

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This commit is contained in:
2Shirt 2023-10-14 19:29:01 -07:00
parent cfd502245c
commit dca6aa7154
Signed by: 2Shirt
GPG key ID: 152FAC923B0E132C
1 changed files with 2 additions and 0 deletions
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2
scripts/wk/hw/diags.py
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@ -562,9 +562,11 @@ def cpu_test_sysbench(state: State, test_object, test_mode=False) -> None:
# 0 == Completed w/out issue
# -2 == Stopped with INT signal
# -15 == Stopped with TERM signal
test_object.failed = True
test_object.set_status('Failed')
test_object.report.append(f' Failed with return code: {proc.returncode}')
else:
test_object.passed = True
test_object.set_status('Passed')
test_object.report.append(' Completed without issue.')
state.update_progress_file()