From dca6aa71545b42b082e97c655add84fdedae7478 Mon Sep 17 00:00:00 2001
From: 2Shirt <2xShirt@gmail.com>
Date: Sat, 14 Oct 2023 19:29:01 -0700
Subject: [PATCH] Add missing Sysbench pass/fail logic

---
 scripts/wk/hw/diags.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/scripts/wk/hw/diags.py b/scripts/wk/hw/diags.py
index 6da3331d..ae9739bc 100644
--- a/scripts/wk/hw/diags.py
+++ b/scripts/wk/hw/diags.py
@@ -562,9 +562,11 @@ def cpu_test_sysbench(state: State, test_object, test_mode=False) -> None:
     #  0  == Completed w/out issue
     # -2  == Stopped with INT signal
     # -15 == Stopped with TERM signal
+    test_object.failed = True
     test_object.set_status('Failed')
     test_object.report.append(f'  Failed with return code: {proc.returncode}')
   else:
+    test_object.passed = True
     test_object.set_status('Passed')
     test_object.report.append('  Completed without issue.')
   state.update_progress_file()