diff --git a/scripts/wk/cfg/hw.py b/scripts/wk/cfg/hw.py
index f97e3acc..26163047 100644
--- a/scripts/wk/cfg/hw.py
+++ b/scripts/wk/cfg/hw.py
@@ -63,27 +63,27 @@ SMC_IDS = {
   # Sources:  https://github.com/beltex/SMCKit/blob/master/SMCKit/SMC.swift
   #           http://www.opensource.apple.com/source/net_snmp/
   #           https://github.com/jedda/OSX-Monitoring-Tools
-  'TA0P': {'CPU Temp': False, 'Source': 'Ambient temp'},
+  'TA0P': {'CPU Temp': False, 'Source': 'Ambient'},
   'TA0S': {'CPU Temp': False, 'Source': 'PCIE Slot 1 Ambient'},
-  'TA1P': {'CPU Temp': False, 'Source': 'Ambient temp'},
+  'TA1P': {'CPU Temp': False, 'Source': 'Ambient'},
   'TA1S': {'CPU Temp': False, 'Source': 'PCIE Slot 1 PCB'},
   'TA2S': {'CPU Temp': False, 'Source': 'PCIE Slot 2 Ambient'},
   'TA3S': {'CPU Temp': False, 'Source': 'PCIE Slot 2 PCB'},
-  'TC0C': {'CPU Temp': True,  'Source': 'CPU Core 0'},
-  'TC0D': {'CPU Temp': True,  'Source': 'CPU die temp'},
-  'TC0H': {'CPU Temp': True,  'Source': 'CPU heatsink temp'},
-  'TC0P': {'CPU Temp': True,  'Source': 'CPU Ambient 1'},
-  'TC1C': {'CPU Temp': True,  'Source': 'CPU Core 1'},
-  'TC1P': {'CPU Temp': True,  'Source': 'CPU Ambient 2'},
-  'TC2C': {'CPU Temp': True,  'Source': 'CPU B Core 0'},
-  'TC2P': {'CPU Temp': True,  'Source': 'CPU B Ambient 1'},
-  'TC3C': {'CPU Temp': True,  'Source': 'CPU B Core 1'},
-  'TC3P': {'CPU Temp': True,  'Source': 'CPU B Ambient 2'},
+  'TC0C': {'CPU Temp': True,  'Source': 'CPU Core 1'},
+  'TC0D': {'CPU Temp': True,  'Source': 'CPU Diode'},
+  'TC0H': {'CPU Temp': True,  'Source': 'CPU Heatsink'},
+  'TC0P': {'CPU Temp': True,  'Source': 'CPU Proximity'},
+  'TC1C': {'CPU Temp': True,  'Source': 'CPU Core 2'},
+  'TC1P': {'CPU Temp': True,  'Source': 'CPU Proximity 2'},
+  'TC2C': {'CPU Temp': True,  'Source': 'CPU Core 3'},
+  'TC2P': {'CPU Temp': True,  'Source': 'CPU Proximity 3'},
+  'TC3C': {'CPU Temp': True,  'Source': 'CPU Core 4'},
+  'TC3P': {'CPU Temp': True,  'Source': 'CPU Proximity 4'},
   'TCAC': {'CPU Temp': True,  'Source': 'CPU core from PCECI'},
   'TCAH': {'CPU Temp': True,  'Source': 'CPU HeatSink'},
   'TCBC': {'CPU Temp': True,  'Source': 'CPU B core from PCECI'},
   'TCBH': {'CPU Temp': True,  'Source': 'CPU HeatSink'},
-  'Te1P': {'CPU Temp': False, 'Source': 'PCIE ambient temp'},
+  'Te1P': {'CPU Temp': False, 'Source': 'PCIE Ambient'},
   'Te1S': {'CPU Temp': False, 'Source': 'PCIE slot 1'},
   'Te2S': {'CPU Temp': False, 'Source': 'PCIE slot 2'},
   'Te3S': {'CPU Temp': False, 'Source': 'PCIE slot 3'},